The present disclosure relates to a solid-state image pickup element typified by a CMOS (Complementary Metal Oxide Semiconductor) image sensor, and a camera system using the same.
The same processes as those in a general CMOS type integrated circuit can be used for manufacture of a CMOS image sensor. In addition, the CMOS image sensor can be driven by using a simple power source. Moreover, an analog circuit and a logic circuit can be mixed with each other within the same chip by utilizing the CMOS process.
For this reason, the CMOS image sensor has plural large merits such that it is possible to reduce the number of peripheral ICs.
A 1-channel (ch) output using a Floating Diffusion (FD) amplifier having an FD is the mainstream in an output circuit of a CCD.
On the other hand, the CMOS image sensor has an FD amplifier every pixel. Also, a column parallel output type such that certain one row within a pixel array is selected and pixel signals are simultaneously read out from pixels belonging to the certain one row thus selected in a column direction is the mainstream in an output of the CMOS image sensor.
The reason for this is because it is difficult to obtain a sufficient driving ability in the FD amplifier disposed within the pixel, and therefore it is necessary to reduce a data rate and thus parallel processing is claimed to be advantageous.
The various kinds of pixel signal reading-out (outputting) circuits of the column parallel output type CMOS image sensors have been really proposed.
One of the most advanced forms of the pixel signal reading-out (outputting) circuits is the pixel signal outputting circuit of a type in which it includes an Analog-to-Digital converter (hereinafter referred to as “an ADC” for short) every column, and takes out a pixel signal as a digital signal.
The CMOS image sensor equipped with such a column parallel type ADC, for example, is disclosed in a non-patent document of W. Yang et al. (W. Yang et al., “An integrated 800×600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304 to 305, Feb., 1999) or Japanese Patent Laid-Open No. 2005-278135.
FIG. 1 is a block diagram, partly in circuit, showing an example of a configuration of a solid-state image pickup element (CMOS image sensor) equipped with a column parallel ADC.
The solid-state image pickup element 1, as shown in FIG. 1, includes a pixel portion 2, a vertical scanning circuit 3, a horizontal transfer scanning circuit 4, and a column processing circuit group 5 composed of an ADC group.
In addition, the solid-state image pickup element 1 includes a Digital-to-Analog converter (hereinafter referred to as “a DAC” for short) 6, and an amplifier circuit (S/A) 7.
The pixel potion 2 is configured by disposing unit pixels 21 each including a photodiode (photoelectric conversion element) and an intra-pixel amplifier in a matrix.
Plural column processing circuits 51 each composing the ADC every column are disposed in plural columns in the column processing circuit group 5.
Each of the column processing circuits (ADCs) 51 includes a comparator 51-1. In this case, the comparator 51-1 compares an analog signal obtained from the pixels every row line via a vertical signal line with a reference signal RAMP (having an electric potential Vslop) as a signal which has a ramp waveform (RAMP) and is obtained by changing a reference signal generated from the DAC 6 in a staircase pattern.
In addition, each of the column processing circuits 51 includes a counter latch (memory) 51-2 for counting a comparison time in the comparator 51-1, and holding therein a count result.
The column processing circuit 51 has an n-bit digital signal converting function. Also, the plural column processing circuits 51 are disposed so as to correspond to the vertical signal lines (column lines) 8-1 to 8-n, respectively, thereby configuring a column parallel ADC block.
Output terminals of the counter latches (memories) 51-2, for example, are connected to a horizontal transfer line 9 having a k-bits width.
Also, k amplifier circuits 7 corresponding to the horizontal transfer line 9 are disposed.
FIG. 2 is a timing chart explaining an operation of the solid-state image pickup element 1 shown in FIG. 1.
In each of the column processing circuits (ADCs) 51, the analog signal (having an electric potential Vsl) read to the vertical signal line 8 is compared with the reference signal RAMP (having an electric potential Vslop) which is changed in the staircase pattern in the comparator 51-1 disposed every column.
At this time, in each of the column processing circuits (ADCs) 51, counting is carried out in the counter latch 51-2 until the analog potential Vsl and the reference signal RAMP (having the electric potential Vslop) intersect in level with each other, so that the output signal from the comparator 51-1 is inverted in polarity. Also, an electric potential (of an analog signal) Vsl of the vertical signal line 8 is converted (AD-converted) into a digital signal.
The AD conversion is carried out twice in one reading operation.
In the first round of the AD conversion, reset levels (P-phase) of unit pixels 21 are read to the vertical signal lines 8-1 to 8-n, respectively, thereby carrying out the AD conversion.
The dispersion in the pixels is contained in the reset levels (P-phase).
In the second round of the AD conversion, signals obtained through the photoelectric conversion in the unit pixels 21 are read to the vertical signal lines 8-1 to 8-n (D-phase), respectively, thereby carrying out the AD conversion.
Since the dispersion in the pixels is contained in the D-phase as well, (D-phase level-P-phase level) is carried out, thereby making it possible to realize Correlated Double Sampling (CDS).
The signals converted into the digital signals are recorded in the counter latches 51-2, respectively, and are then read to the amplifier circuit 7 through the horizontal transfer line 9 in order by the horizontal (column) transfer scanning circuit 4 to be finally outputted.
The column parallel outputting processing is executed in the manner as described above.
Now, Japanese Patent Laid-Open No. 2005-278135 proposes a technique for reducing the noise in the digital processing in the CMOS image sensor having such a column ADC configuration.
With this technique, as shown in FIG. 1, the sampling of the reset level (P-phase), and the sampling of the signal level (D-phase) are each continuously carried out plural times, and the sampling result is either integrated or averaged, thereby enhancing an S/N ratio.